This invention relates to circuits and methods for driving a dynamic random access memory (DRAM) sense amplifier. More particularly, this invention relates to circuits and methods for driving a DRAM sense amplifier having low threshold voltage p-channel metal-oxide semiconductor (PMOS) field-effect transistors.
Known DRAM circuits generally include the following: a plurality of dynamic memory cells each operative to store digital data (i.e., digital data bit “1” or digital data bit “0”); word lines operative is to “select” and “deselect” the memory cells; and digital lines operative to read, write, and refresh the digital data of selected memory cells. Additionally, DRAM circuits include sense amplifier circuitry, sense amplifier driver circuitry, and various other peripheral circuitry (e.g., equalization and pre-charge circuitry, write circuitry, word line decoders, digital line decoders, etc.) that control DRAM operation.
Generally speaking, DRAM sense amplifier driver circuitry “activates” a sense amplifier during read, write, and refresh operations. An activated sense amplifier amplifies (i.e., increases) a differential voltage between a complimentary pair of digital lines to a full digital logic separation (i.e., a full digital “0” on the first digital line of the complimentary pair and a full digital “1” on the second digital line of the complimentary pair). Alternatively, DRAM sense amplifier driver circuitry “deactivates” the sense amplifier during DRAM standby mode (i.e., DRAM circuit operation pending a read, write, or refresh operation). A deactivated sense amplifier does not amplify and preferably does not affect the voltage potential between the complimentary pair of digital lines.
As feature size (e.g., transistor channel length) is reduced, an increased number of transistors can be included in an integrated circuit (IC) chip. For DRAM technology, an increased number of transistors can advantageously provide, for example, increased data storage capacity in a DRAM circuit (i.e., additional memory cells). However, because the number of transistors on an IC chip is directly proportional to power consumption by the IC chip, any significant increase in the number of transistors on an IC chip is preferably accompanied by a reduction in the voltage supplied to the IC chip, which reduces power consumption by the IC chip. Such a voltage reduction is generally accompanied by a decrease in the threshold voltage of each transistor (i.e., voltage at which a transistor becomes conductive or turns “ON”).
Known DRAM sense amplifier driver circuits are not well-suited for driving DRAM sense amplifiers having low threshold voltage PMOS transistors. Such known driver circuits cause significant sub-threshold current loss through sense amplifiers having low threshold voltage PMOS transistors. Sub-threshold current loss through a DRAM sense amplifier undesirably increases power consumption, increases the time required for a read, write, and refresh operation, and can cause erroneous reading and refreshing of digital data.
In view of the foregoing, it would be desirable to provide improved circuits and methods for driving a DRAM sense amplifier having low threshold voltage PMOS transistors.